Worst Case Transistor
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![Worst Case Transistor (a) Sleep transistor with passively clamped bias [7]. (b) Programming ...](https://www.researchgate.net/publication/2983357/figure/fig4/AS:405631447126017@1473721481380/a-Sleep-transistor-with-passively-clamped-bias-7-b-Programming-for-worst-case-cell.png)




































































![Worst Case Transistor XOR-XNOR gate using 8 transistors in [5] | Download Scientific Diagram](https://www.researchgate.net/profile/Rajeev-Kumar-62/publication/216446658/figure/fig2/AS:678254860046338@1538719968219/Worst-case-delay-of-different-XOR-circuit_Q320.jpg)


























